The small program:
'****************
Freeduino as TestRig for HiSpeed ISP over Cat5 cable of 15 meter
************************
'The
START .....
$baud =
38400 'for
debug only
$crystal =
16000000
$regfile =
"m168def.dat"
$hwstack
= 40
' default use 32 for the hardware
stack
$swstack =
10 '
default use 10 for the SW stack
$framesize
= 40
' default use 40 for the frame
space
'Timer1
setup Mode 8 Phase and freq correct pwm, ICR1=top
Tccr1a
= &B10000000
Tccr1b
= &B00010001
Set
Ddrb.1
'enable
output of OC1A
Capture1 =
7
Ocr1a = 1
Do
Loop
The schematic it looks like this:
Picture 1: Ch1 shows OC1A from the AVR
R1 and R2 are in place, C1=0pF Ch2: measured over R2. The pulse amplitude is about 2V, so barely enough to meet the spec of TTL or HCT |
|
Nothing changed, except that Ch1 now measures what is at the beginning of the cable | |
Oooompf
R2 is removed, so we lack termination. The pulse at the end of the cable travels back to the source, and that's the second pulse on Ch1 Nasty huh ? Oh, BTW: using a narrow pulse is TEH way to go for these experiments. |
|
O my goodness:
The transmission line (the cable) is driven HARD .... and no termination by R2 How is that for a digital signal ?! |
|
But look what happens if the line is terminated with 100 Ohm ! | |
And now as a bonus experiment: R1=22 Ohm, a small capacitor of 220pF reduces the slewrate, R2 in place as terminator ( I'll be back - AS) |
To get a good insight, I sticked with the narrow pulse. Btw, narrow is a relative term of course. In terms of ISP it's narrow ;-) |
|
But since ISP takes place at a lower frequency I added tests with 160 kHz, 50% dutycycle. | |
The 10 nF looked nicer, but the smaller the capacitor, the less we have to worry on the load it represents to the programmer and target-AVR (Miso-line that is) | |
Clean shit huh ? | |
Using 1 nF : it will still work fine for ISP but it's a bit too small IMO | |
..... and the overshoots on the output, and the initial load for the source (programmer or target AVR) |
Oh, and for the sake of completeness: the program |
'****************
Freeduino as TestRig for HiSpeed ISP over Cat5 cable of 15 meter
************************ Print
"New settings ..."
Input "Top = " , Top Input "Pulse_width = " , Pulse_width Capture1 = Top Ocr1a = Pulse_width
|
As could be expected: no problemo ! | |
A bit more rounded off | |
Hmmm, this shows the mismatch: Mark the yellow signal |
|
Now terminated with Termisistor= 100 Ohm with 2n2 in series |